1. Field of the Invention
The invention relates to a semiconductor process, and, more particularly, to a metal salicide-chemical mechanical polishing (CMP)--metal salicide semiconductor process by which a thicker metal salicide layer is formed on gates to prevent an unacceptable increased gate contact resistance which results from over etching during the etching of shallow contact windows on gates and causes low device efficiencies.
2. Description of the Related Art
Generally, different material layers are formed on a base substrate by depositing and etching in a semiconductor process. As a result, the surface of the substrate on which devices have been already formed is rough, i.e., different positions on the surface of the substrate have different heights. Therefore, etching contact windows having different depths at the same time can not be avoided. In a deep sub-micron semiconductor process, wherein the dimensions of contact windows continue to shrink, Ti self-aligned salicide (Ti salicide) technology is adopted and a chemical mechanical polishing (CMP) method is employed. This results in an increasing severity of the over etching problem that causes material loss inside shallow contact windows during the etching of shallow contact windows.
Referring to FIGS. 1A to 1C, a semiconductor wafer contact window process according to the prior art is illustrated. FIG. 1A shows a part of a cross-sectional view of a semiconductor wafer wherein a metal salicide process and a CMP method for planarization have already been completed. Shown are semiconductor substrate 1, field oxide 2, spacers 3, silicon layer 4 (for example, a poly-silicon layer), Ti salicide (TiSi.sub.2) layer 5 and interlayer dielectric layer 6.
Referring to FIG. 1B, photoresistor layer 7 is deposited over semiconductor substrate 1 of FIG. 1A and a contact window pattern is defined by a photolithography technology. The result shown in FIG. 1B includes a .DELTA.X distance representing the difference between the depths of two expected contact windows for poly-silicon layer 4 and a source (drain) (not shown), respectively.
Referring next to FIG. 1C, shallow contact window 11 is formed in dielectric layer 6 using anisotropic etching. Due to the two expected contact windows having depth difference .DELTA.X, when Ti salicide layer 5 inside shallow contact window 11 begins to be etched during an etching process, there is still the .DELTA.X thickness in deep contact window 12 left for further etching. Therefore, when deep contact window 12 is etched to the end, Ti salicide layer 5 on poly-silicon layer 4, and even poly-silicon layer 4, are seriously etched, resulting in an unacceptable increased gate contact. Typically, Ti salicide layer 5 on polysilicon layer 4 is thinner and more unstable than that on a single-silicon layer, so the selectivity of interlayer dielectric 6 to Ti salicide layer 5 is not preferable.